
;-------------------------------------------------- 
; SX1 SDRAM n FLASH latency patch v1.0 
;    1.0 
; changes bootcore of Z1 firmware image 
; by Vovan888 (vovan@oslik.ru) 18.01.2006 
; oslik.ru 
; dedicated to Z-team and overclockers.ru 
; !! ! DANGER !! ! Possible data loss ! 
; !! !  !! !    ! 
;   10   3Dmark 

; reduce CAS latency time for SDRAM from 3 to 2 
;  CAS latency  3  2 
;0x0A44 
replace:3710A0E3241080E50A00A0E3010050E2000050E3:27 

;    
; change timings for FLASH (drive A, C, Z) 
;     ....:70202100.... (  ): 
; 7 - (0..F) - Number of wait states for asynchronous read operation 
; 2 - (0..F) - For read accesses, number of wait states for page 
; mode ROM reads within a page. For write accesses 
; the length of WE pulse duration. 
replace:902021007050210039110000:7020210070202100 

;   SDRAM 
; change timings for SDRAM 
; SDRAM_FREQUENCY from SDF1 to SDF2 (see spru673.pdf, page 55 for details) 
;    (SDF)  0 (  ,   ) 
;  3 - (  ,   ) 
;    1 (SDF1).   0,  .  2 - . 
;     . 
; SDF 1 is default 
; Slow ..........Fast 
;      SDF0 SDF1 SDF2 SDF3 
; Trc     9    5    3    2 
; Tras    5    3    2    2 
; Trp     3    2    2    2 
; Trcd    3    2    2    2 
; Trrd    2    2    2    2 
; Trsc    2    2    2    - 
; 0x1258 

;    ( !) 
; to SDF0: 
;replace:B0F00501B4F0050100CEFEFF:B0F00500B4F00500 
; to SDF2 
;replace:B0F00501B4F0050100CEFEFF:B0F00502B4F00502 
; to SDF3 
;replace:B0F00501B4F0050100CEFEFF:B0F00503B4F00503 
;-------------------------------------------------- 